The present invention relates to a semiconductor memory device like a dynamic random access memory (DRAM).
In a known semiconductor memory device, e.g., DRAM, in particular, data stored on its memory cell is usually lost due to its own physical properties after a certain period of time has passed. To avoid such an unfavorable situation, refreshing is needed. And to perform this refreshing a t regular intervals, a system utilizing a DRAM should control the refresh operation. Accordingly, a DRAM requiring refreshing is not so easy to handle as other semiconductor memory devices requiring no refreshing.
Hereinafter, a known semiconductor memory device will be described. FIG. 25 is a block diagram illustrating a configuration for a main part of a known semiconductor memory device. As shown in FIG. 25, the memory device includes address buffer 3, row decoder 4, column decoder 5, sense amplifier 6, input/output buffer 7, memory array 8, refresh counter 9 and command decoder 10. A set of addresses, consisting of row and column addresses, are externally input through the address buffer 3 and decoded by the row and column decoders 4 and 5, respectively. It should be noted that these column and row addresses externally input will be herein called an "external address" collectively. The sense amplifier 6 is provided to amplify the data stored on a memory cell. The input/output buffer 7 is provided to input and output data therethrough. In the memory array 8, a great number of memory cells, each requiring refreshing, are arranged in columns and rows. The refresh counter 9 is a collection of counters that are provided in such a number as needed to decode row addresses. The command decoder 10 decodes an externally input command to generate a refresh enable signal during refreshing. In response to the refresh enable signal, the refresh counter 9 counts the number of row addresses provided one by one.
The known semiconductor memory device with such a configuration performs refreshing responsive to a refresh command/REF that has been input to the device. On decoding the refresh command /REF, the command decoder 10 outputs the refresh enable signal to the refresh counter 9. In response, the refresh counter 9 starts counting the pulses of the refresh enable signal to find associated row addresses internally. And memory cells, which have been selected by the row decoder 4 by reference to the row addresses, are refreshed as a result. This operation should be performed a predetermined number of times within a predefined refresh cycle.
In the known configuration, however, the system outside of the DRAM should include a refresh controller to meet the requirements of refreshing. In addition, while the DRAM is performing the refresh operation, the system controls accesses to the DRAM so that the DRAM cannot be externally accessed. For these reasons, the DRAM is not so easy to handle as other semiconductor memory devices requiring no refreshing.
To cope with such a problem, a DRAM, which looks like requiring no refreshing, was proposed as disclosed in Japanese Laid-Open Publication No. 9-190689, in which two transistors are provided for a single memory cell and one of these two transistors is exclusively used for refreshing. A DRAM, including memory cells with such a two-transistor, one-capacitor construction, needs a chip area twice larger than a DRAM, including memory cells with a normal one-transistor, one-capacitor construction, does. Nevertheless, a DRAM of the former type still operates at the same frequency as a DRAM of the latter type. Thus, this alternative construction is not advantageous in cost effectiveness.